1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and especially relates to a split-gate nonvolatile semiconductor memory device.
2. Description of Related Art
A split-gate nonvolatile semiconductor memory device is known as a nonvolatile semiconductor memory device. For example, Japanese Laid-Open Patent Applications JP-P2001-230330A, JP-P2000-286348A, and JP-P2001-085543A, disclose the split-gate nonvolatile semiconductor memory devices, each of which has an erasing gate.
FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device disclosed in JP-P2001-230330A. This nonvolatile semiconductor memory device includes: a floating gate 120 formed on a semiconductor substrate 110 via a gate insulating film 112; an erasing gate 140 formed on the floating gate 120 via insulating films 113 and 114; a control gate (not shown in the figure) formed on one side wall portion of the floating gate 120, the insulating films 113 and 114, and the erasing gate 140 via a insulating film (not shown in the figure) formed to coat the floating gate 120, the insulating films 113 and 114, and the erasing gate 140; and a diffusion region (not shown in the figure) formed on a surface layer of the substrate 110 so as to adjoin the floating gate 120 or the control gate. This nonvolatile semiconductor memory device is provided with the erasing gate 140 directly above the floating gate 120. In the figure, sharpened portions (sharpened portions 121) in upper portions of both ends of the floating gate 120 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 121 to the erasing gate 140.
FIG. 2 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device disclosed in JP-P2000-286348A. This nonvolatile semiconductor memory device includes a floating gate 220 and a control gate 230 on a semiconductor substrate 210 having a first diffusion region 251 and a second diffusion region 252. This nonvolatile semiconductor memory device is characterized by having an erasing gate 240 which is formed so as to adjoin the floating gates 220 of adjoining memory cells via a tunnel oxide film 214 and is connected to a first diffusion region 251 with keeping a certain interval. This nonvolatile semiconductor memory device provides the erasing gate 240 on a side of the floating gate 220. In the figure, a sharpened portion (a sharpened portion 221) on an erasing gate 240 side of the floating gate 220 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 221 to the erasing gate 240.
FIG. 3 is a cross-sectional view showing a configuration of a split-gate memory cell disclosed in JP-P2001-085543A. This split-gate memory cell includes a source region 351 and a drain region 352 formed on a semiconductor substrate 310, a channel region sandwiched by the source region 351 and the drain region 352, a floating gate electrode 320 formed on the channel region via a floating gate insulating film 311, a control gate electrode 330 formed on the channel region via a control gate insulating film 312, and an erasing gate electrode 340 formed on the floating gate electrode 320 via an erasing gate insulating film 315. The floating gate insulating film 311 and the erasing gate insulating film 315 include independently separated insulating film, respectively. The nonvolatile semiconductor memory device is characterized in that the floating gate electrode 320 is formed in a self-aligning manner with respect to the control gate electrode 330. In the figure, a sharpened portion (a sharpened portion 321) on an erasing gate 340 side of the floating gate 320 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 321 to the erasing gate 340.
In a nonvolatile semiconductor memory device, its operation speed is increasingly high in these years. For example, as for the nonvolatile semiconductor memory device incorporated in a microcomputer, since an operation speed of the microcomputer itself has been increasingly high, the operation speed of the nonvolatile semiconductor memory device is strongly required to be high. In addition, the nonvolatile semiconductor memory device is required to satisfy requirements of finely miniaturizing a circuit and of lowering an operating voltage.
The inventor has now discovered following facts.
A technique of JP-P2001-230330A discloses a structure in which the erasing gate 140 (a portion facing the sharpened portion 121) is embedded between the two floating gates 120 as shown in FIG. 1. For this reason, the erasing gate 140 and the floating gate 120 face each other at surfaces (a surface 140a and a surface 120a). In this case where the erasing gate 140 and the floating gate 120 face each other at the surfaces, there is a problem that a voltage applied between the erasing fate 140 and the floating gate 120 becomes small in the erasing operation because a coupling capacity is large. For this reason, there is a problem that the erasing operation at a high speed cannot be expected.
Techniques of JP-P2000-286348A and JP-P2001-085543A have a same problem. Specifically, in the technique of JP-P2000-286348A, since the erasing gate 240 and the floating gate 220 face each other at surfaces (a surface 240a and a surface 220a) as shown in FIG. 2, a coupling capacity is large. Similarly, in the technique of JP-P2001-085543A, since the erasing gate 340 and the floating gate 320 face each other at surfaces (a surface 340a and a surface 320a) as shown in FIG. 3, a coupling capacity is large. For this reason, there is a problem that the erasing operation at a high speed cannot be expected.